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13 commits

Author SHA1 Message Date
cjkas
cbeb56d336 fix: review fixes for the ESP32-P4 build
- The pre-v3 build is for chips before v2.0, not v3.0: the esp32p4_es
  libraries stop at v1.99.  The CI label and comments say so, and that no
  build runs on v2.x or v3.00.
- A save refuses a clock mode the chip can't use: ProtoSettings takes
  CLKMode 0-ETH_CLOCK_ID_MAX, 0 only on the P4.  Before, 1-3 saved and
  then stopped Ethernet at the next start.  A range of one value reads
  "must be 0".
- Tests for the pin limit (54 taken, 55 refused) and the clock limits.
- The web UI's P4 pins leave out strapping pin 36 too.
- The preset says ESP32-P4-WIFI6-POE-ETH, the board's name.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-29 20:10:36 +01:00
cjkas
dfb003d2f7 build: add the ESP32-P4 (#29)
For boards such as Waveshare's ESP32-P4-WIFI6-POE-ETH: WiFi through the
board's ESP32-C6 on SDIO (esp-hosted), Ethernet on the P4's RMII MAC with
an IP101.  Not tested on a device: no P4 board was at hand.

- platformio.ini: env esp32p4 (esp32-p4_r3, chip v3.01+) and esp32p4es
  (esp32-p4, the esp32p4_es libraries, chips before v2.0).  An image runs
  on one of the two only, so each has its own release files, chip models
  "p4" and "p4es".  Both keep the OTA slot: at level 2 they leave about
  128 KB of it.
- Ethernet clock mode: stored as eth_clock_id_t in the ESP32's numbering
  and translated by name, like the PHY id.  The P4's eth_clock_mode_t is
  the IDF's emac_rmii_clock_mode_t, whose 0 is a deprecated default; only
  clock in (GPIO 50) translates there.
- P4 Ethernet defaults: the Waveshare wiring (IP101 as TLK110, address 1,
  MDC 31, MDIO 52, reset 51), board type 8.  The ESP32's put MDIO on an
  SDIO pin.
- Settings take pins up to GPIO 54, the P4's last, instead of 48.
- Radio defaults: SPI 32/33/27, CSN 46 (the framework's Waveshare
  variant), TX 2, RX 3.
- Web UI: a Waveshare ESP32-P4-ETH preset, the P4's clock mode, pin lists
  up to GPIO 54 without the pins the C6 link, Ethernet, USB and UART0 use.
- CI builds and releases both, with their ELFs; bootloader at 0x2000.
- ADR 0003: amended.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-29 19:41:39 +01:00
cjkas
8600c5e811 ci: attach each board's firmware ELF to releases
A crash log on a release build couldn't be decoded: the release had only
the .bin files, and the ELF was a 5-day CI artifact of other runs.  The
panic in #31 names "ELF file SHA256: f85f409205c11d1b" and no copy of that
file exists.

Each release now gets SomfyController.ino.<chip>.elf.zip, built in the
same job as the .bin it decodes.  Beside the ELF is its .sha256: the .bin
embeds that hash, and the panic prints its first digits, so a log shows
which build it came from.  The bug report form asks for the whole panic
and says how to decode it.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-29 18:53:45 +01:00
cjkas
0437cd2a88 fix: review fixes for the C5 build
- ADR 0003: the C5 gets its own consequence instead of sitting in the
  ADR 0006 amendment. It names the single-slot table, the chip revision
  minimum (v1.0, CONFIG_ESP32C5_REV_MIN_FULL=100) and the longer WiFi
  scans with 5 GHz.
- platformio.ini: the [esp32] comment names the C5 and C6 as released
  debug builds; the C5 comment no longer repeats the C6's.
- Transceiver: the C5 comment says why TX and RX are 4 and 5.
- CI: the addr_fs comment names both partition tables.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-28 22:49:42 +01:00
cjkas
298045ec99 build: add the ESP32-C5
The C5 builds like the C6: a debug build with one 3 MB app slot, so it
updates over USB. At CORE_DEBUG_LEVEL=2 its image left 3.4 KB of the
1.5 MB OTA slot, under CI's 8 KB.

- platformio.ini: env esp32c5 (esp32-c5-devkitc-1).
- Chip model "c5", so the updater and releases name its files
  SomfyController.*.esp32c5.bin.
- Radio defaults: the framework's SPI pins (CSN 6, MOSI 8, MISO 9,
  SCK 10), TX 4, RX 5.
- Web UI: GPIO 0-28, without 13-14 (USB) and 15-22 (flash, PSRAM).
- CI builds and releases it; its bootloader sits at 0x2000.
- ADR 0003: amended.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-28 21:51:15 +01:00
cjkas
d596291677 build: bring back the ESP32-C3 build
With the old API gone, the C3 image is 1,498,512 bytes at
CORE_DEBUG_LEVEL=2 and leaves 72.6 KB of its 1.5 MB OTA slot. It was
76.5 KB over when ESP-IDF 5.5 dropped it.

- platformio.ini: env esp32c3, single core, esp32_3MB.csv, level 2.
- CI builds and releases it with the other chips.
- ADR 0003: amended.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-28 21:31:10 +01:00
cjkas
4f7067388a ci: pin pioarduino 6.2.0
6.2.0.post1 reports itself as 6.2.0-post.1, which the pinned platform's
">=6.2.0" requirement reads as a pre-release, so every ESP32 build
fails at its first pio run.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-26 22:11:26 +01:00
cjkas
99c6019431 feat: web UI protocol 2 client layer, JS and CSS bundles (step 2a)
- data-src/js: ProtoSchema (schema from the sync, short keys and names,
  defaults, cached by hash), ProtoModel (rooms, shades, groups, repeaters,
  header and status from the sync and the events) and ProtoClient (/ws,
  hello, sync with next, op() as a Promise of its reply, events, feeds,
  reconnect). Nothing uses them yet: 2b moves the UI onto them.
- minify.py joins js/*.js and index.js into index.js, and the three CSS
  files into app.css, so a page load opens fewer connections.
- test/js: node --test on the three modules, replaying the recorded
  fixtures; a CI job runs it and the firmware build waits for it.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-25 15:00:23 +01:00
cjkas
a1622e652d build: move to pioarduino 55.03.312 (Arduino 3.3.12, ESP-IDF 5.5)
IDF 4.4 gets no more security fixes, and the planned RMT radio needs
IDF 5's RMT driver.  See docs/adr/0003-pioarduino-idf55.md.

- Every env on one pinned pioarduino release.  C6 drops its own
  library list and flags but stays a debug build on huge_app.
- Release envs build at CORE_DEBUG_LEVEL=2 so the ESP32 image fits its
  1.5 MB OTA slot (17 KB free); debug envs stay at 3.
- Drop the C3: its image is 76.5 KB over the OTA slot on IDF 5.5.
- CI installs pioarduino's Core and checks firmware.bin against the app
  partition, failing under 8 KB free.  PlatformIO's "Flash:" figure
  reads ~45 KB low and passed a C3 image that doesn't fit.
- esp_task_wdt_reconfigure(): on 3.x the core already starts the watchdog
  and esp_task_wdt_init() fails, so the C6 build kept the 5 s default.
- An updated firmware is kept only once it has run 60 s with the
  network up; a reset before then rolls back to the previous one.
- ETH.begin() takes the 3.x argument order; Arduino 2.x branches gone.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-19 22:05:22 +02:00
cjkas
aa23b4624d ci: run native unit tests before firmware builds
Adds a "Unit tests" job running pio test -e native on ubuntu-latest.
The firmware build matrix waits for it, so a failing test also stops
release uploads.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-11 12:54:48 +02:00
cjkas
b785dc2967 build only on open PRs 2026-04-04 12:50:26 +02:00
cjkas
d15b05cfbd Preserve littlefs image before firmware build wipes it out 2026-04-04 12:44:57 +02:00
cjkas
15d5b064d4 improve release build 2026-04-04 12:40:14 +02:00
Renamed from .github/workflows/release.yaml (Browse further)