mirror of
https://github.com/rstrouse/ESPSomfy-RTS.git
synced 2026-10-31 13:52:15 +01:00
dfb003d2f7
For boards such as Waveshare's ESP32-P4-WIFI6-POE-ETH: WiFi through the board's ESP32-C6 on SDIO (esp-hosted), Ethernet on the P4's RMII MAC with an IP101. Not tested on a device: no P4 board was at hand. - platformio.ini: env esp32p4 (esp32-p4_r3, chip v3.01+) and esp32p4es (esp32-p4, the esp32p4_es libraries, chips before v2.0). An image runs on one of the two only, so each has its own release files, chip models "p4" and "p4es". Both keep the OTA slot: at level 2 they leave about 128 KB of it. - Ethernet clock mode: stored as eth_clock_id_t in the ESP32's numbering and translated by name, like the PHY id. The P4's eth_clock_mode_t is the IDF's emac_rmii_clock_mode_t, whose 0 is a deprecated default; only clock in (GPIO 50) translates there. - P4 Ethernet defaults: the Waveshare wiring (IP101 as TLK110, address 1, MDC 31, MDIO 52, reset 51), board type 8. The ESP32's put MDIO on an SDIO pin. - Settings take pins up to GPIO 54, the P4's last, instead of 48. - Radio defaults: SPI 32/33/27, CSN 46 (the framework's Waveshare variant), TX 2, RX 3. - Web UI: a Waveshare ESP32-P4-ETH preset, the P4's clock mode, pin lists up to GPIO 54 without the pins the C6 link, Ethernet, USB and UART0 use. - CI builds and releases both, with their ELFs; bootloader at 0x2000. - ADR 0003: amended. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
100 lines
4.1 KiB
C++
100 lines
4.1 KiB
C++
#include <unity.h>
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// As on the original ESP32, so the translation is built.
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#define CONFIG_ETH_USE_ESP32_EMAC 1
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#include "EthPhy.h"
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void setUp() {}
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void tearDown() {}
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static eth_phy_type_t translate(eth_phy_id_t id) {
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eth_phy_type_t type = ETH_PHY_MAX;
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TEST_ASSERT_TRUE(ethPhyType(static_cast<uint8_t>(id), type));
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return type;
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}
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/*********************************************************************
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* Stored ids
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********************************************************************/
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static void test_ids_match_stored_values() {
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// NVS, backups and the web UI hold these numbers. Changing one moves
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// every existing Ethernet board to another chip.
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TEST_ASSERT_EQUAL_UINT8(0, static_cast<uint8_t>(eth_phy_id_t::LAN8720));
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TEST_ASSERT_EQUAL_UINT8(1, static_cast<uint8_t>(eth_phy_id_t::TLK110));
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TEST_ASSERT_EQUAL_UINT8(2, static_cast<uint8_t>(eth_phy_id_t::RTL8201));
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TEST_ASSERT_EQUAL_UINT8(3, static_cast<uint8_t>(eth_phy_id_t::DP83848));
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TEST_ASSERT_EQUAL_UINT8(4, static_cast<uint8_t>(eth_phy_id_t::DM9051));
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TEST_ASSERT_EQUAL_UINT8(5, static_cast<uint8_t>(eth_phy_id_t::KSZ8041));
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TEST_ASSERT_EQUAL_UINT8(6, static_cast<uint8_t>(eth_phy_id_t::KSZ8081));
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}
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/*********************************************************************
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* ethPhyType
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********************************************************************/
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static void test_translates_each_rmii_chip_by_name() {
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TEST_ASSERT_EQUAL(ETH_PHY_LAN8720, translate(eth_phy_id_t::LAN8720));
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TEST_ASSERT_EQUAL(ETH_PHY_TLK110, translate(eth_phy_id_t::TLK110));
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TEST_ASSERT_EQUAL(ETH_PHY_RTL8201, translate(eth_phy_id_t::RTL8201));
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TEST_ASSERT_EQUAL(ETH_PHY_DP83848, translate(eth_phy_id_t::DP83848));
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TEST_ASSERT_EQUAL(ETH_PHY_KSZ8041, translate(eth_phy_id_t::KSZ8041));
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TEST_ASSERT_EQUAL(ETH_PHY_KSZ8081, translate(eth_phy_id_t::KSZ8081));
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}
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static void test_lan8720_is_not_the_framework_zero() {
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// The default board stores 0. Arduino 3.x's 0 is ETH_PHY_GENERIC.
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TEST_ASSERT_NOT_EQUAL(0, translate(eth_phy_id_t::LAN8720));
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}
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static void test_rejects_dm9051() {
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eth_phy_type_t type = ETH_PHY_MAX;
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TEST_ASSERT_FALSE(ethPhyType(static_cast<uint8_t>(eth_phy_id_t::DM9051), type));
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}
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static void test_rejects_unknown_ids() {
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eth_phy_type_t type = ETH_PHY_MAX;
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TEST_ASSERT_FALSE(ethPhyType(7, type));
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TEST_ASSERT_FALSE(ethPhyType(255, type));
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}
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/*********************************************************************
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* Clock modes
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********************************************************************/
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static void test_clock_ids_match_stored_values() {
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TEST_ASSERT_EQUAL_UINT8(0, static_cast<uint8_t>(eth_clock_id_t::GPIO0_IN));
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TEST_ASSERT_EQUAL_UINT8(1, static_cast<uint8_t>(eth_clock_id_t::GPIO0_OUT));
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TEST_ASSERT_EQUAL_UINT8(2, static_cast<uint8_t>(eth_clock_id_t::GPIO16_OUT));
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TEST_ASSERT_EQUAL_UINT8(3, static_cast<uint8_t>(eth_clock_id_t::GPIO17_OUT));
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}
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static void test_translates_each_clock_mode() {
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eth_clock_mode_t mode;
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TEST_ASSERT_TRUE(ethClockMode(0, mode));
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TEST_ASSERT_EQUAL(ETH_CLOCK_GPIO0_IN, mode);
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TEST_ASSERT_TRUE(ethClockMode(1, mode));
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TEST_ASSERT_EQUAL(ETH_CLOCK_GPIO0_OUT, mode);
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TEST_ASSERT_TRUE(ethClockMode(2, mode));
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TEST_ASSERT_EQUAL(ETH_CLOCK_GPIO16_OUT, mode);
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TEST_ASSERT_TRUE(ethClockMode(3, mode));
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TEST_ASSERT_EQUAL(ETH_CLOCK_GPIO17_OUT, mode);
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}
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static void test_rejects_unknown_clock_ids() {
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eth_clock_mode_t mode;
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TEST_ASSERT_FALSE(ethClockMode(4, mode));
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TEST_ASSERT_FALSE(ethClockMode(255, mode));
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}
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static void test_clock_pins() {
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TEST_ASSERT_EQUAL_INT8(0, ethClockPin(0));
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TEST_ASSERT_EQUAL_INT8(0, ethClockPin(1));
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TEST_ASSERT_EQUAL_INT8(16, ethClockPin(2));
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TEST_ASSERT_EQUAL_INT8(17, ethClockPin(3));
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TEST_ASSERT_EQUAL_INT8(-1, ethClockPin(4));
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}
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int main(int, char **) {
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UNITY_BEGIN();
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RUN_TEST(test_ids_match_stored_values);
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RUN_TEST(test_translates_each_rmii_chip_by_name);
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RUN_TEST(test_lan8720_is_not_the_framework_zero);
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RUN_TEST(test_rejects_dm9051);
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RUN_TEST(test_rejects_unknown_ids);
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RUN_TEST(test_clock_ids_match_stored_values);
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RUN_TEST(test_translates_each_clock_mode);
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RUN_TEST(test_rejects_unknown_clock_ids);
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RUN_TEST(test_clock_pins);
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return UNITY_END();
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}
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