aaribaud/ESPSomfy-RTS
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fix: review fixes for the ESP32-P4 build

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- The pre-v3 build is for chips before v2.0, not v3.0: the esp32p4_es
  libraries stop at v1.99.  The CI label and comments say so, and that no
  build runs on v2.x or v3.00.
- A save refuses a clock mode the chip can't use: ProtoSettings takes
  CLKMode 0-ETH_CLOCK_ID_MAX, 0 only on the P4.  Before, 1-3 saved and
  then stopped Ethernet at the next start.  A range of one value reads
  "must be 0".
- Tests for the pin limit (54 taken, 55 refused) and the clock limits.
- The web UI's P4 pins leave out strapping pin 36 too.
- The preset says ESP32-P4-WIFI6-POE-ETH, the board's name.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
This commit is contained in:
cjkas 2026-10-29 20:10:36 +01:00
parent dfb003d2f7
commit cbeb56d336
10 changed files with 45 additions and 11 deletions
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7
data-src/index.js
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@ -1579,7 +1579,7 @@ class Wifi {
{ val: 5, label: 'wESP32 v7+ - Silicognition', clk: 0, ct: 2, addr: 0, pwr: -1, mdc: 16, mdio: 17 },
{ val: 6, label: 'wESP32 < v7 - Silicognition', clk: 0, ct: 0, addr: 0, pwr: -1, mdc: 16, mdio: 17 },
{ val: 1, label: 'WT32-ETH01 - Wireless Tag', clk: 0, ct: 0, addr: 1, pwr: 16, mdc: 23, mdio: 18 },
{ val: 8, label: 'ESP32-P4-ETH - Waveshare', clk: 0, ct: 1, addr: 1, pwr: 51, mdc: 31, mdio: 52, p4: true }
{ val: 8, label: 'ESP32-P4-WIFI6-POE-ETH - Waveshare', clk: 0, ct: 1, addr: 1, pwr: 51, mdc: 31, mdio: 52, p4: true }
];
ethClockModes = [{ val: 0, label: 'GPIO0 IN' }, { val: 1, label: 'GPIO0 OUT' }, { val: 2, label: 'GPIO16 OUT' }, { val: 3, label: 'GPIO17 OUT' }];
// The P4 takes the clock in on GPIO 50 only (eth_clock_id_t in EthPhy.h).
@ -2735,8 +2735,9 @@ class Somfy {
{ name: 'c5', maxPins: 28, inputs: [13, 14, 15, 16, 17, 18, 19, 20, 21, 22], outputs: [13, 14, 15, 16, 17, 18, 19, 20, 21, 22] },
{ name: 'c6', maxPins: 23, inputs: [], outputs: [] },
// Without the C6's SDIO link (14-19, 54), USB Serial/JTAG (24, 25),
// Ethernet (28-31, 34, 35, 49-52) and UART0 (37, 38).
{ name: 'p4', maxPins: 54, inputs: [14, 15, 16, 17, 18, 19, 24, 25, 28, 29, 30, 31, 34, 35, 37, 38, 49, 50, 51, 52, 54], outputs: [14, 15, 16, 17, 18, 19, 24, 25, 28, 29, 30, 31, 34, 35, 37, 38, 49, 50, 51, 52, 54] }
// Ethernet (28-31, 34, 35, 49-52), UART0 (37, 38) and the strapping
// pins (34-38).
{ name: 'p4', maxPins: 54, inputs: [14, 15, 16, 17, 18, 19, 24, 25, 28, 29, 30, 31, 34, 35, 36, 37, 38, 49, 50, 51, 52, 54], outputs: [14, 15, 16, 17, 18, 19, 24, 25, 28, 29, 30, 31, 34, 35, 36, 37, 38, 49, 50, 51, 52, 54] }
];
loadPins(type, sel, opt) {