diff --git a/.github/workflows/build.yaml b/.github/workflows/build.yaml
index d4b1f33..730b265 100644
--- a/.github/workflows/build.yaml
+++ b/.github/workflows/build.yaml
@@ -60,8 +60,9 @@ jobs:
         # fwname: firmware-only binary for OTA updates
         # obname: onboard image (bootloader + partitions + firmware + littlefs merged)
         #         for flashing a new chip via USB/serial
-        # addr_bootloader: chip-dependent (ESP32: 0x1000, S3/C3/C6: 0x0)
-        # addr_fs: must match spiffs/littlefs offset in esp32_3MB.csv
+        # addr_bootloader: chip-dependent (ESP32: 0x1000, S3/C3/C6: 0x0, C5: 0x2000)
+        # addr_fs: must match the spiffs offset in the env's partition table
+        #          (0x310000 in both esp32_3MB.csv and esp32_huge_app.csv)
         include:
           - env: esp32dev
             name: ESP32
@@ -87,6 +88,14 @@ jobs:
             fwname: SomfyController.ino.esp32c3.bin
             fsname: SomfyController.littlefs.esp32c3.bin
             obname: SomfyController.onboard.esp32c3.bin
+          - env: esp32c5
+            name: ESP32-C5
+            chip: ESP32-C5
+            addr_bootloader: "0x2000"
+            addr_fs: "0x310000"
+            fwname: SomfyController.ino.esp32c5.bin
+            fsname: SomfyController.littlefs.esp32c5.bin
+            obname: SomfyController.onboard.esp32c5.bin
           - env: esp32c6
             name: ESP32-C6
             chip: ESP32-C6
diff --git a/data-src/index.js b/data-src/index.js
index be90fed..cecd83c 100644
--- a/data-src/index.js
+++ b/data-src/index.js
@@ -2719,6 +2719,7 @@ class Somfy {
         { name: 's2', maxPins: 46, inputs: [0, 19, 20, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 45], outputs: [0, 19, 20, 26, 27, 28, 29, 30, 31, 32, 45, 46]},
         { name: 's3', maxPins: 48, inputs: [19, 20, 22, 23, 24, 25, 27, 28, 29, 30, 31, 32], outputs: [19, 20, 22, 23, 24, 25, 27, 28, 29, 30, 31, 32] },
         { name: 'c3', maxPins: 21, inputs: [11, 12, 13, 14, 15, 16, 17, 18, 19, 20], outputs: [11, 12, 13, 14, 15, 16, 17, 21] },
+        { name: 'c5', maxPins: 28, inputs: [13, 14, 15, 16, 17, 18, 19, 20, 21, 22], outputs: [13, 14, 15, 16, 17, 18, 19, 20, 21, 22] },
         { name: 'c6', maxPins: 23, inputs: [], outputs: [] }
     ];
 
diff --git a/docs/adr/0003-pioarduino-idf55.md b/docs/adr/0003-pioarduino-idf55.md
index 96fbc8b..fb87a35 100644
--- a/docs/adr/0003-pioarduino-idf55.md
+++ b/docs/adr/0003-pioarduino-idf55.md
@@ -14,7 +14,8 @@ We moved every firmware env from `espressif32 @ 6.13.0` (Arduino 2.0.17 on ESP-I
 - **No more C3 builds.** Its image grows by 214 KB to 1,651,216 bytes, 76.5 KB over the OTA slot even at level 2. C3 boards stay on the 3.0.x releases.
 
   > **Amended by [ADR 0006](0006-two-security-modes-eleven-http-routes.md) (4.0.0).** The C3 builds again. Without the old API (ports 8080 and 8081), its image is 1,498,512 bytes at level 2 and leaves 72.6 KB of the OTA slot. It runs on chip revision v0.3 or later only: the framework's C3 libraries are built with `CONFIG_ESP32C3_REV_MIN_3`. Its default radio pins moved off GPIO 12-17, which hold the SPI flash.
+- **The C5 is updated over USB.** New in 4.0.0. At level 2 its image left 3.4 KB of the OTA slot, under CI's 8 KB, so like the C6 it is released as a debug build with one 3 MB app slot (`esp32_huge_app.csv`), which no OTA can write. The framework's C5 libraries run on chip revision v1.0 or later only (`CONFIG_ESP32C5_REV_MIN_FULL=100`). Its WiFi has 5 GHz too, so the passive scans for the configured network (`src/ESPNetwork.cpp`, 300 ms a channel) cover about 38 channels instead of 13: about 11 s instead of 4 s, depending on the country's channels.
 - **Ethernet PHY ids are ours.** Arduino 3.x renumbered `eth_phy_type_t` (`ETH_PHY_GENERIC` is 0). NVS, backups and the web UI keep the Arduino 2.x numbers as `eth_phy_id_t` (`src/EthPhy.h`), translated by name when Ethernet starts. Never cast a stored id to the framework enum.
-- **Ethernet only on the original ESP32.** Arduino 3.x has the RMII MAC API only where `CONFIG_ETH_USE_ESP32_EMAC` is set. S3, C3 and C6 build without Ethernet.
+- **Ethernet only on the original ESP32.** Arduino 3.x has the RMII MAC API only where `CONFIG_ETH_USE_ESP32_EMAC` is set. S3, C3, C5 and C6 build without Ethernet.
 - **Updates roll back until proven.** We override the core's `verifyRollbackLater()` hook to return true, and `loop()` marks the new firmware valid once it has run 60 s and the network is up. A reset before then boots the previous firmware. The LittleFS image an update wrote stays, so the old firmware runs with the new web UI.
 - **Tooling.** pioarduino needs its own Core fork (`pip install pioarduino`, the pioarduino IDE extension in VS Code), which it installs into `~/.platformio/penv` in place of PlatformIO Core.
diff --git a/platformio.ini b/platformio.ini
index aaed9a4..de180a2 100644
--- a/platformio.ini
+++ b/platformio.ini
@@ -33,6 +33,7 @@ extra_scripts =
 board_build.filesystem = littlefs
 ; Each env adds a CORE_DEBUG_LEVEL: 2 (warnings) for release builds, which
 ; only fit the 1.5 MB OTA slot without the info logs, 3 for debug builds.
+; The C5 and C6 release their debug build, which has a 3 MB slot.
 build_flags =
 	-DCONFIG_ESP_COREDUMP_ENABLE_TO_FLASH=1
 	-DCONFIG_ESP_COREDUMP_DATA_FORMAT_ELF=1
@@ -103,6 +104,17 @@ build_flags =
 	${esp32.build_flags}
 	-DCORE_DEBUG_LEVEL=2
 
+; Released like the C6 below.  At level 2 its image left 3.4 KB of the
+; 1.5 MB OTA slot, under CI's 8 KB.
+[env:esp32c5]
+extends = esp32
+board = esp32-c5-devkitc-1
+build_type = debug
+board_build.partitions = esp32_huge_app.csv
+build_flags =
+	${esp32.build_flags}
+	-DCORE_DEBUG_LEVEL=3
+
 ; Released as a debug build with one 3 MB app slot, so C6 boards update over
 ; USB, not OTA.
 [env:esp32c6]
diff --git a/src/ConfigSettings.cpp b/src/ConfigSettings.cpp
index 8b23346..47d2d7e 100644
--- a/src/ConfigSettings.cpp
+++ b/src/ConfigSettings.cpp
@@ -135,6 +135,11 @@ bool ConfigSettings::begin() {
     case esp_chip_model_t::CHIP_ESP32C3:
       strcpy(this->chipModel, "c3");
       break;
+    #ifdef CONFIG_IDF_TARGET_ESP32C5
+    case esp_chip_model_t::CHIP_ESP32C5:
+      strcpy(this->chipModel, "c5");
+      break;
+    #endif
     #ifdef CONFIG_IDF_TARGET_ESP32C6
     case esp_chip_model_t::CHIP_ESP32C6:
       strcpy(this->chipModel, "c6");
diff --git a/src/ConfigSettings.h b/src/ConfigSettings.h
index 81c5838..a0b1e6b 100644
--- a/src/ConfigSettings.h
+++ b/src/ConfigSettings.h
@@ -164,7 +164,7 @@ class ConfigSettings: BaseSettings {
     char hostname[32] = "ESPSomfyRTS";
     char chipModel[10] = "ESP32";
     // Whether the partition table has a second app slot for /updateFirmware
-    // to write.  Builds with one 3 MB slot (C6, debug) are flashed over USB.
+    // to write.  Builds with one 3 MB slot (C5, C6, debug) are flashed over USB.
     bool hasOtaSlot = true;
     conn_types_t connType = conn_types_t::unset;
     appver_t fwVersion;
diff --git a/src/EthPhy.h b/src/EthPhy.h
index 6b2ec46..004b5b4 100644
--- a/src/EthPhy.h
+++ b/src/EthPhy.h
@@ -5,8 +5,8 @@
 #include <sdkconfig.h>
 #endif
 
-// Ethernet needs the RMII MAC, which only the original ESP32 has.  The C3, S3
-// and C6 build without it.
+// Ethernet needs the RMII MAC, which only the original ESP32 has.  The C3, C5,
+// S3 and C6 build without it.
 #if defined(CONFIG_ETH_USE_ESP32_EMAC) && CONFIG_ETH_USE_ESP32_EMAC
 #define HAS_ETHERNET 1
 #else
diff --git a/src/Transceiver.cpp b/src/Transceiver.cpp
index 48ca4cf..c66280c 100644
--- a/src/Transceiver.cpp
+++ b/src/Transceiver.cpp
@@ -483,6 +483,19 @@ void transceiver_config_t::load() {
         this->SCKPin = 4;
         this->CSNPin = 7;
         break;
+#ifdef CONFIG_IDF_TARGET_ESP32C5
+      case esp_chip_model_t::CHIP_ESP32C5:
+        // The framework's default SPI pins (variants/esp32c5).  TX and RX take
+        // 4 and 5, the LP UART's pins, which nothing here uses; 2, 3, 7 and
+        // 25-28 are strapping pins and 11-22 hold UART0, USB and the flash.
+        this->TXPin = 4;
+        this->RXPin = 5;
+        this->MOSIPin = 8;
+        this->MISOPin = 9;
+        this->SCKPin = 10;
+        this->CSNPin = 6;
+        break;
+#endif
 #ifdef CONFIG_IDF_TARGET_ESP32C6
       case esp_chip_model_t::CHIP_ESP32C6:
       // Pinout applicable for the ESP32-C6-WROOM-1 module (ESP32-C6-DevKitC-1-N4)
diff --git a/src/Utils.h b/src/Utils.h
index f01cf05..ffd3483 100644
--- a/src/Utils.h
+++ b/src/Utils.h
@@ -85,7 +85,7 @@ const char *wifiAuthModeName(uint8_t authMode);
 bool otaProven(bool networkUp, unsigned long uptimeMs, unsigned long minUptimeMs);
 // A release asset's name: "SomfyController.<kind>.esp32<chipModel>.bin", kind
 // "ino" for the firmware or "littlefs" for the web UI image, chipModel as in
-// ConfigSettings ("" for the ESP32, "s3", "c3", "c6").
+// ConfigSettings ("" for the ESP32, "s3", "c3", "c5", "c6").
 void releaseAssetName(char *buf, size_t size, const char *kind, const char *chipModel);
 // A coredump backtrace as " 0x%08x" per frame.  bt holds maxFrames entries and
 // depth is how many the dump claims are valid.
diff --git a/test/test_utils/test_utils.cpp b/test/test_utils/test_utils.cpp
index 040d34f..c95a91e 100644
--- a/test/test_utils/test_utils.cpp
+++ b/test/test_utils/test_utils.cpp
@@ -280,6 +280,8 @@ static void test_releaseAssetName_matches_the_release_workflow() {
   TEST_ASSERT_EQUAL_STRING("SomfyController.littlefs.esp32s3.bin", buf);
   releaseAssetName(buf, sizeof(buf), "ino", "c3");
   TEST_ASSERT_EQUAL_STRING("SomfyController.ino.esp32c3.bin", buf);
+  releaseAssetName(buf, sizeof(buf), "ino", "c5");
+  TEST_ASSERT_EQUAL_STRING("SomfyController.ino.esp32c5.bin", buf);
   releaseAssetName(buf, sizeof(buf), "littlefs", "c6");
   TEST_ASSERT_EQUAL_STRING("SomfyController.littlefs.esp32c6.bin", buf);
 }