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fix: review fixes for the C3 build

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- The C3's default radio pins were GPIO 12-17, which hold its SPI flash.
  They are now the framework's SPI pins (SCK 4, MISO 5, MOSI 6, CSN 7)
  with TX 10 and RX 3. A board with pins saved keeps them.
- ADR 0003: the amendment links ADR 0006, says the C3 needs chip
  revision v0.3 or later (CONFIG_ESP32C3_REV_MIN_3), and the Ethernet
  bullet names the C3.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
This commit is contained in:
cjkas 2026-10-28 22:32:37 +01:00
parent a43f5aaaad
commit 527215d21a
2 changed files with 10 additions and 8 deletions
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14
src/Transceiver.cpp
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@ -474,12 +474,14 @@ void transceiver_config_t::load() {
this->CSNPin = 34;
break;
case esp_chip_model_t::CHIP_ESP32C3:
this->TXPin = 13;
this->RXPin = 12;
this->MOSIPin = 16;
this->MISOPin = 17;
this->SCKPin = 15;
this->CSNPin = 14;
// The framework's default SPI pins (variants/esp32c3). 12-17 hold the
// SPI flash, and 2, 8 and 9 are strapping pins.
this->TXPin = 10;
this->RXPin = 3;
this->MOSIPin = 6;
this->MISOPin = 5;
this->SCKPin = 4;
this->CSNPin = 7;
break;
#ifdef CONFIG_IDF_TARGET_ESP32C6
case esp_chip_model_t::CHIP_ESP32C6: