fix: review fixes for the C5 build

- ADR 0003: the C5 gets its own consequence instead of sitting in the
  ADR 0006 amendment. It names the single-slot table, the chip revision
  minimum (v1.0, CONFIG_ESP32C5_REV_MIN_FULL=100) and the longer WiFi
  scans with 5 GHz.
- platformio.ini: the [esp32] comment names the C5 and C6 as released
  debug builds; the C5 comment no longer repeats the C6's.
- Transceiver: the C5 comment says why TX and RX are 4 and 5.
- CI: the addr_fs comment names both partition tables.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

.github/workflows/build.yaml

@@ -61,7 +61,8 @@ jobs:
         # obname: onboard image (bootloader + partitions + firmware + littlefs merged)
         #         for flashing a new chip via USB/serial
         # addr_bootloader: chip-dependent (ESP32: 0x1000, S3/C3/C6: 0x0, C5: 0x2000)
-        # addr_fs: must match spiffs/littlefs offset in esp32_3MB.csv
+        # addr_fs: must match the spiffs offset in the env's partition table
+        #          (0x310000 in both esp32_3MB.csv and esp32_huge_app.csv)
         include:
           - env: esp32dev
             name: ESP32

docs/adr/0003-pioarduino-idf55.md

@@ -13,7 +13,8 @@ We moved every firmware env from `espressif32 @ 6.13.0` (Arduino 2.0.17 on ESP-I
 - **Firmware size.** The ESP32 image grows from 1,382,640 bytes (v3.0.14) to 1,555,472 at `CORE_DEBUG_LEVEL=2`, leaving 17 KB of the 1.5 MB OTA slot. At level 3 it doesn't fit, so release envs build at level 2 (warnings and errors) and debug envs stay at 3. PlatformIO's "Flash:" figure counts ELF sections, not the image, and reads about 45 KB low, so CI checks `firmware.bin` against the app partition and fails under 8 KB free (`.github/size_check.py`).
 - **No more C3 builds.** Its image grows by 214 KB to 1,651,216 bytes, 76.5 KB over the OTA slot even at level 2. C3 boards stay on the 3.0.x releases.
 
-  > **Amended by [ADR 0006](0006-two-security-modes-eleven-http-routes.md) (4.0.0).** The C3 builds again. Without the old API (ports 8080 and 8081), its image is 1,498,512 bytes at level 2 and leaves 72.6 KB of the OTA slot. It runs on chip revision v0.3 or later only: the framework's C3 libraries are built with `CONFIG_ESP32C3_REV_MIN_3`. Its default radio pins moved off GPIO 12-17, which hold the SPI flash. The C5 is new in 4.0.0 and builds like the C6: a debug build with one 3 MB app slot, updated over USB, since at level 2 its image left only 3.4 KB of the OTA slot.
+  > **Amended by [ADR 0006](0006-two-security-modes-eleven-http-routes.md) (4.0.0).** The C3 builds again. Without the old API (ports 8080 and 8081), its image is 1,498,512 bytes at level 2 and leaves 72.6 KB of the OTA slot. It runs on chip revision v0.3 or later only: the framework's C3 libraries are built with `CONFIG_ESP32C3_REV_MIN_3`. Its default radio pins moved off GPIO 12-17, which hold the SPI flash.
+- **The C5 is updated over USB.** New in 4.0.0. At level 2 its image left 3.4 KB of the OTA slot, under CI's 8 KB, so like the C6 it is released as a debug build with one 3 MB app slot (`esp32_huge_app.csv`), which no OTA can write. The framework's C5 libraries run on chip revision v1.0 or later only (`CONFIG_ESP32C5_REV_MIN_FULL=100`). Its WiFi has 5 GHz too, so the passive scans for the configured network (`src/ESPNetwork.cpp`, 300 ms a channel) cover about 38 channels instead of 13: about 11 s instead of 4 s, depending on the country's channels.
 - **Ethernet PHY ids are ours.** Arduino 3.x renumbered `eth_phy_type_t` (`ETH_PHY_GENERIC` is 0). NVS, backups and the web UI keep the Arduino 2.x numbers as `eth_phy_id_t` (`src/EthPhy.h`), translated by name when Ethernet starts. Never cast a stored id to the framework enum.
 - **Ethernet only on the original ESP32.** Arduino 3.x has the RMII MAC API only where `CONFIG_ETH_USE_ESP32_EMAC` is set. S3, C3, C5 and C6 build without Ethernet.
 - **Updates roll back until proven.** We override the core's `verifyRollbackLater()` hook to return true, and `loop()` marks the new firmware valid once it has run 60 s and the network is up. A reset before then boots the previous firmware. The LittleFS image an update wrote stays, so the old firmware runs with the new web UI.

platformio.ini

@@ -33,6 +33,7 @@ extra_scripts =
 board_build.filesystem = littlefs
 ; Each env adds a CORE_DEBUG_LEVEL: 2 (warnings) for release builds, which
 ; only fit the 1.5 MB OTA slot without the info logs, 3 for debug builds.
+; The C5 and C6 release their debug build, which has a 3 MB slot.
 build_flags =
 	-DCONFIG_ESP_COREDUMP_ENABLE_TO_FLASH=1
 	-DCONFIG_ESP_COREDUMP_DATA_FORMAT_ELF=1
@@ -103,9 +104,8 @@ build_flags =
 	${esp32.build_flags}
 	-DCORE_DEBUG_LEVEL=2
 
-; Released as a debug build with one 3 MB app slot, so C5 and C6 boards
-; update over USB, not OTA.  The C5's image leaves 3.4 KB of the 1.5 MB OTA
-; slot even at level 2.
+; Released like the C6 below.  At level 2 its image left 3.4 KB of the
+; 1.5 MB OTA slot, under CI's 8 KB.
 [env:esp32c5]
 extends = esp32
 board = esp32-c5-devkitc-1

src/Transceiver.cpp

@@ -485,8 +485,9 @@ void transceiver_config_t::load() {
         break;
 #ifdef CONFIG_IDF_TARGET_ESP32C5
       case esp_chip_model_t::CHIP_ESP32C5:
-        // The framework's default SPI pins (variants/esp32c5).  4 and 5 aren't
-        // strapping pins.
+        // The framework's default SPI pins (variants/esp32c5).  TX and RX take
+        // 4 and 5, the LP UART's pins, which nothing here uses; 2, 3, 7 and
+        // 25-28 are strapping pins and 11-22 hold UART0, USB and the flash.
         this->TXPin = 4;
         this->RXPin = 5;
         this->MOSIPin = 8;