fix: review fixes for the C5 build

- ADR 0003: the C5 gets its own consequence instead of sitting in the
  ADR 0006 amendment. It names the single-slot table, the chip revision
  minimum (v1.0, CONFIG_ESP32C5_REV_MIN_FULL=100) and the longer WiFi
  scans with 5 GHz.
- platformio.ini: the [esp32] comment names the C5 and C6 as released
  debug builds; the C5 comment no longer repeats the C6's.
- Transceiver: the C5 comment says why TX and RX are 4 and 5.
- CI: the addr_fs comment names both partition tables.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

src/Transceiver.cpp

@@ -485,8 +485,9 @@ void transceiver_config_t::load() {
         break;
 #ifdef CONFIG_IDF_TARGET_ESP32C5
       case esp_chip_model_t::CHIP_ESP32C5:
-        // The framework's default SPI pins (variants/esp32c5).  4 and 5 aren't
-        // strapping pins.
+        // The framework's default SPI pins (variants/esp32c5).  TX and RX take
+        // 4 and 5, the LP UART's pins, which nothing here uses; 2, 3, 7 and
+        // 25-28 are strapping pins and 11-22 hold UART0, USB and the flash.
         this->TXPin = 4;
         this->RXPin = 5;
         this->MOSIPin = 8;