fix: review fixes for the C5 build

- ADR 0003: the C5 gets its own consequence instead of sitting in the
  ADR 0006 amendment. It names the single-slot table, the chip revision
  minimum (v1.0, CONFIG_ESP32C5_REV_MIN_FULL=100) and the longer WiFi
  scans with 5 GHz.
- platformio.ini: the [esp32] comment names the C5 and C6 as released
  debug builds; the C5 comment no longer repeats the C6's.
- Transceiver: the C5 comment says why TX and RX are 4 and 5.
- CI: the addr_fs comment names both partition tables.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

platformio.ini

@@ -33,6 +33,7 @@ extra_scripts =
 board_build.filesystem = littlefs
 ; Each env adds a CORE_DEBUG_LEVEL: 2 (warnings) for release builds, which
 ; only fit the 1.5 MB OTA slot without the info logs, 3 for debug builds.
+; The C5 and C6 release their debug build, which has a 3 MB slot.
 build_flags =
 	-DCONFIG_ESP_COREDUMP_ENABLE_TO_FLASH=1
 	-DCONFIG_ESP_COREDUMP_DATA_FORMAT_ELF=1
@@ -103,9 +104,8 @@ build_flags =
 	${esp32.build_flags}
 	-DCORE_DEBUG_LEVEL=2
 
-; Released as a debug build with one 3 MB app slot, so C5 and C6 boards
-; update over USB, not OTA.  The C5's image leaves 3.4 KB of the 1.5 MB OTA
-; slot even at level 2.
+; Released like the C6 below.  At level 2 its image left 3.4 KB of the
+; 1.5 MB OTA slot, under CI's 8 KB.
 [env:esp32c5]
 extends = esp32
 board = esp32-c5-devkitc-1